4. Down to the wire

Class Activity

ACTIVITY 1

Task 74. Read the passage and guess what the text is about.

Introduction TEXT 1A:

Implementing nanometer-scale ICs begins and ends with wires. Wires are so dominant that little is known about a design’s performance or manufacturability without them. In fact, nanometer design strategies that are not clearly focused on rapid wire creation, optimization, and analysis are destined to fail.

This paper describes the requirements for an effective, reliable IC implementation platform for the 90 nm process node and beyond. It begins with a description of the central role wires play in nanometer design and why traditional linear design flows are insufficient. It then describes a new continuous convergence methodology, which has proven highly valuable at 0.13 micron and will be absolutely necessary at 90 nm.

Next, the paper describes the key implementation, analysis, and database technologies needed to enable this methodology. Implementing nanometer designs requires nanometer routers that optimize wire creation for both performance and manufacturability. Verifying nanometer designs requires nanometer analysis tools that accurately model physical effects as they would occur in the target silicon. Efficiently representing these designs – most of which will be large digital designs with critical analog circuitry – requires unified nanometer databases with massive capacity and efficient extensibility.

Wires must be the centerpiece of any nanometer methodology. Without such a methodology, design teams will not be able to create massively complex nanometer ICs in a timeframe of relevance.

Task 75. Organizing your thoughts:

1. What does implementing nanometer scale IC begin and end with?

2. Which requirements does this text describe?

3. What is necessary to implement nanometric design?

4. What must be the center piece of any nanometer methodology?

Task 76. Study the sentences where the following words and word combinations are used:

wiring delay – задержка проводной связи

overall delay – полная задержка

signal integrity (SI) – целостный сигнал

information retrieval (IR) – поиск информации

“sign off” – дать знак окончания передачи

wire capacitance – емкостное сопротивление проводов

capacitive coupling – ёмкостная связь

grid spacing – сетчатый интервал

overall power supply voltage – полное напряжение электропитания

gate – затвор

Task 77. Read the following text carefully paying attention to the italicized words and word combinations and try to understand the contents of the text:

BASIC TEXT 1B:

WIRING DOMINATES NANOMETER DESIGN

In nanometer design, wiring delay accounts for the vast majority of overall delay. It is well known that delay has been shifting from gates to wires for quite some time. As shown in Figure 10, wiring delay exceeds gate delay at 0.18 micron and below in aluminum processes, and at 0.13 micron and below in copper. By 90 nm, wiring delay will account for some 75% of the overall delay. As a result, design teams need to shift their focus from logic optimization to wire optimization.

Figure 10: Wire and gate delay in Al and Cu

THE CHANGING NATURE OF DELAY

In addition to dominating overall delay, nanometer design exacerbates physical effects that introduce substantial delay – notably signal integrity (SI) and IR (voltage) drop. These effects can be considerable even at 0.18 micron. By 0.13 micron, “sign-off” timing analysis tools miss numerous SI- and IR drop-based degradations that are comparable in magnitude to the nominal timing and much more difficult to predict. Yet, many design teams continue to use delay calculations based on over-simplified models (e.g., lumped capacitance) down to 0.13 micron. Doing so results in both reduced performance – due to high margins – and excessive, time-consuming design iterations. At 90 nm, timing analysis that does not include SI and IR drop effects is essentially meaningless.

Delay is a function of wire loading and wire drive. At 0.25 micron and above, the primary wire capacitance is due to coupling to electrical ground and is largely proportionate to wire length; doubling the wire length doubles the capacitance. Steiner, or global, routing estimates predict the wire length based on placement.

As process geometries decrease, the primary capacitive coupling on a given wire moves to its neighboring wires.

Capacitance depends on the local wire geometry and, in many cases, to the actual signals on neighboring wires. As an example, Figure 11 shows delay variation at 0.18 micron due to capacitive coupling for signals at 1X and 2X grid spacings. The variation is up to +/-30 % for 1 mm wires and +80 %/-60 % for 3 mm wires.

At 0.18 micron, cross coupling affects only high-performance designs significantly. By 90 nm, it will significantly affect all designs. Since capacitance is no longer strictly proportional to wire length at nanometer geometries, detailed routing is required for accurate timing analysis.

Figure 11: Crosstalk introduces substantial delay variation

Resistance in the power and ground wire networks creates IR drop. Nanometer designs are extremely susceptible to these effects because this resistance increases with decreasing feature sizes. It is further exacerbated when the overall power supply voltage decreases because this also decreases the usable region of the signal transitions. With decreasing supply voltage, gate delays and noise susceptibility increase. An IR drop from 1.7V to 1.6V is capable of producing delay variations of 50 % or more. One study of designs at 0.18 micron and below showed that 20 % of designs failed on first silicon due to excessive IR drop alone.

Task 78. Fill in the gaps with the correct variants:

1. Wiring ….. accounts for the vast majority of overall delay.

a) retard b) delay c) propagation

2. Wiring delay ….. gate delay at 0.18 micron and below in aluminum processes, and at 0.13 micron and below in copper.

a) exceeds b) retards c) approaches

3. As a result, design teams need to …. their focus from logic optimization to wire optimization.

a) transform b) shift c) lower

4. Nanometer design exacerbates ….. effects that introduce substantial delay.

a) phisical b) chemical c) biological

5. Delay is a function of ….. and wire drive.

a) wire capacitance b)wire drive c) wire loading

Task 79. Match up the words with their definition.

d elay	the distance between two things one of which is higher than other, a sudden fall
wire	the property of a system that enables in to store electrostatic charge
capacitance	metal drawn out into thread
drop	the act of delaying, the state of being delayed

Task 80. Look through the text again and find the following words in the sentences:

1. delay.

2. capacitance.

3. wire capacitance.

4. “sign off” timing analysis tools

5. IR drop.

6. wiring delay.

7. gate delay

Task 81. Organizing your thoughts:

1. What accounts for the vast majority of overall delay?

2. Why does wiring delay exceed gate delay?

3. What is the changing nature of delay?

4. When does cross coupling take place?

5. What is wire capacitance due to?

6. What creates IR drop?

Task 82. Sum up the text using the following plan:

1. Nanometer design domination.

2. Changing nature of delay.

3. Cross coupling.

4. IR drop.

Task 83. Skim the following text and try to understand the subject-matter of it.

TEXT 1C:

THE NEED FOR A NEW DESIGN STRATEGY

Traditional IC implementation approaches are linear in that designs move sequentially through a series of stages – RTL, gates, power planning, placement, clock tree design, routing, and physical analysis. When gates dominate delay, this process is predictable and efficient because performance optimization and analysis iterations occur early in the flow.

As the percentage of delay in the wires increases, linear flows become more unpredictable and inefficient. At 0.18 micron, performance is unknown prior to placement. Using floorplanning and physical synthesis tools, designers can iterate at the placement level to try to find a feasible solution (see Figure 12). When there is no feasible solution, they must go all the way back to change the architecture or logic. The high probability of long iterations greatly reduces predictability, while the iterations themselves greatly reduce efficiency. At 90 nm, performance is unknown prior to detailed routing; this introduces more iterations and longer iterations – and much less predictability and efficiency.

Figure 12: Optimization and analysis iterations by process node

With timing based primarily on wires in nanometer designs, design teams must use methodologies that both generate wires as soon as possible (“time-to-wire”) and minimize full-chip iteration time. Time-to-wire and full-chip iteration time will be the critical metrics for design predictability and efficiency in nanometer design.

Task 84. Find sentences with the following words.

1. IC implementation – применение интегральных схем.

2. logic gate – логический блок.

3. placement – расположение.

4. routing – трассировка.

Task 85. Comprehension check:

1. What is traditional IC implementation approach?

2. Look at Fig.12 and explain optimization and analysis iterations?

3. What does floor planning use?

Task 86. Match up the words with their definitions:

p lacement	the controlling electrode of a field-effect transistor
gate	an answer to, or way to dealing with a problem
route	the way from one place to another
solution	a particular part of space

ACTIVITY 2

Task 87. Skim the following passage and try to understand the subject-matter of it.

TEXT 2A:

PHYSICAL SYNTHESIS IS INSUFFICIENT

Physical synthesis – i.e., concurrent optimization of logic and placement – provides significant advantages at 0.18 micron and 0.13 micron versus traditional wireload-based logic synthesis. Physical synthesis is based on gates, placement, and Manhattan wire estimates which do not include capacitive coupling, metal layer, or detailed routing effects. Since each of these effects has a substantial impact on overall delay, physical synthesis simply does not have adequate information to close timing for nanometer designs.

Despite early market predictions that physical synthesis would replace logic synthesis, design teams use it only to re-optimize gate-level blocks that do not meet timing. In nanometer design, design teams will use physical synthesis only on those blocks that full-chip detailed routing identifies as not meeting timing. At that point, physical synthesis serves as a valuable optimization engine to provide routing with a better starting point for wire optimization.

However, the wires themselves – not the logic or placement – will dictate performance.

Task 88. Comprehension check:

1. What is physical synthesis?

2. What is physical synthesis based on?

3. Where can it be used?

Task 89. Fill in the gaps with the correct variant:

1. Physical synthesis – i.e. concurrent optimization of logic and placement – provides significant ….. at 0.18 micron and 0.13 micron versus traditional wireload – based logic synthesis.

a) advantages b) disadvantages c) opportunities

2. Physical synthesis is based on ….., placement, metal layer or detailed routing effects.

a) placement b) routing c) gates

3. Successful nanometer design methodologies must ….. time-to-wire and full-chip iteration time.

a) maximize b) minimize c) exceed

4. The SVP treats all aspects of the ….. logic, timing, SI, power drop, electromigration (EM), i/o issues and manufacturability

a) construction b) implementation c) design

Task 90. Sum up the text using the following plan.

1. Role of physical synthesis.

2. Beginning of convergence.

3. Nanometer design methodology.

Task 91. Sum up the following passage trying to understand it and give a title to it.

TEXT 2B:

The SVP is key to the continuous convergence methodology. An SVP must be a complete full-chip implementation that is close enough to tapeout quality where designers can accurately assess all relevant aspects of the design.

Yet, it must execute fast enough that designers can iterate rapidly in order to try different implementation directions. A prototype without detailed wiring may help guide logic design, but it will not guide nanometer physical design adequately.

The SVP must support clock structures, power grid, top-level interconnect, and other characteristics of the tapeout design. It must account for all relevant overhead in order to represent a known, physically feasible solution which can guide decisions such as timing-budget and pin assignments – a fully detailed layout with wiring is the only way to guarantee feasible budgets and assignments.

Figure 13: An SVP can serve as a design cockpit

An SVP can serve as a universal cockpit for all tools and functions, combining all aspects of implementation and analysis within a single full-chip environment (see Figure 13). This environment can include implementation functions – floorplanning, placement, physical synthesis, routing, clock-tree synthesis, and power planning – and analysis functions – timing, signal integrity, routability, and power analysis.

Task 92. Comprehension check.

1. What is silicon virtual prototype?

2. What must it support?

3. Which implementation functions can you name?

Task 93. Skim the following passage try to understand the subject-matter of it.

TEXT 2C:

NANOMETER ROUTING REQUIREMENTS

Full-chip detailed routing is the first step in assessing a design’s initial performance. It is also the last step in optimizing the design to meet all of its performance and manufacturing requirements. Nanometer design demands a new type of router that is physics-aware, manufacturing-aware, and has massive capacity and performance.

Above 0.13 micron, only teams with very high-performance designs need to deal with adverse physical effects. Doing so requires extremely expensive manual approaches. By 90 nm, the number and difficulty of problems will increase to the point that it will be completely impractical for most design teams to correct them manually. Instead, design teams will need routers that address physics effects – beginning with SI and IR drop-on-the-fly in order to close timing.

For the most part teams have focused exclusively on timing closure, confident that the result would be manufacturable. Above 0.13 micron, manufacturing procedures such as optical proximity correction (OPC) were performed after generating the fully-routed, and otherwise correct, GDSII. Design teams could also ignore the effects of physical manufacturing processes.

Most design teams run into manufacturability issues for the first time at 0.13 micron. Processes using copper wiring, chemical-mechanical polishing (CMP), and subwavelength lithography lead to exceedingly complex and arcane design rules. Antenna rules, to take one example, require careful handling to avoid via proliferation and minimize wire lengths. Furthermore, foundries continue to change the design rules long after the introduction of a new process in order to optimize time-to-silicon production.

Nanometer routers must explicitly provide for variable width and variable spacing, and they must be capable of adapting to the requirements of copper, multiple vias, OPC, phase-shift masking (PSM), and CMP. Beyond 90 nm, routers will have to optimize the wiring specifically to facilitate manufacturing processes. Nanometer designs will challenge any router that is not designed specifically to account for these advanced process considerations.

At 0.13 micron and above, design teams can perform routing block-by-block, then use a chip-level router to connect the blocks together and perform tasks such as generating the top-level clock tree. Nanometer routers must be capable of working simultaneously at the block-level and chip-level.

The router must be tightly coupled with, and have control over, almost every aspect of the physical realization of the chip, including:

• Routing-optimized placement

• Local logic optimization for timing fixes and area recovery

• Clock tree construction and balancing, including useful skew

• Power grid construction based on IR drop and EM analysis

Nanometer routers must have concurrent access to full parasitic extraction, full-chip static timing analysis (STA), and signal integrity analysis, using these results to guide and to modify routes on-the-fly. High-end design teams must account for the complex interactions between signal, power, and clock routing. For instance, in 90 nm high-performance designs high-speed clock routing must be tightly controlled using techniques such as shielding, track assignment, and topology control. Routing must be integrated with automatic clock tree synthesis and clock timing analysis.

Performing the above, along with supporting variable wire widths and spacings, requires massive capacity and performance. A meaningful benchmark is the ability to route a 10M gate design overnight. Doing so is likely to require multithreading and multiprocessing in order to utilize all computational resources available for the task.

Task 94. Comprehension check:

1. Give the general idea of the whole passage.

2. Figure out manufacturing – aware routing.

3. Describe every aspect of the physical realization of the chip.

Task 95. Skim the passage and sum up delay calculation.

TEXT 2D:

DELAY CALCULATION

Delay calculations performed by today’s “sign-off” timing analyzers are inaccurate. These tools often use oversimplified models (e.g., lumped capacitance) that do not take into consideration dynamic effects on the wires, which in turn have dynamic effects on cell delays. Cell delays change with loading on the gate as well as with coupling effects on nets. The delays are dynamic, not fixed. To be accurate, delay calculation must be based on more than a behavioral abstraction of the cell. It must take current and capacitance characteristics into consideration, down to the transistor level. Cell delay calculation based on lumped capacitance simply is not accurate enough for highfrequency circuits. Nanometer delay calculation must be based on SI and IR drop (see Figure 14).

Figure 14: Nanometer delay calculation with SI and IR drop

Hierarchical delay calculation is also important in nanometer design. Simplistic, conservative timing models at hierarchical boundaries increase margins. Delay calculations must correctly model paths that cross hierarchical boundaries to maintain accuracy.

Task 96. Find the sentences with the following words:

1. “sign-off” timing – подача знака на отключение времени

2. delay calculation – расчет задержки

3. cell delay calculations – задержка расчетов элементов

Task 97. Which of the following do you think is true or false?

1. Delay calculations performed today’s sign off timing analysers are inaccurate.

2. Chip delays change with loading on the gate as well as with coupling effects on nets.

3. The delays are intermediate, not fixed.

Task 98. Study the following words and word combinations in the following sentences:

“sign-off” timing – подача знака на отключение времени

delay calculation – расчет задержки

cell delay calculations – задержка расчетов элементов

Task 99. Skim the text and try to get its main idea.

TEXT 2 E:

NANOMETER PHYSICAL ANALYSIS REQUIREMENTS

The right database is more important than ever in nanometer design, with its massively complex chips, elaborate physical requirements, arcane manufacturing requirements, and all that is still unknown. The majority of nanometer designs will be digital/mixed-signal ICs (i.e., large digital designs with critical analog circuitry) making it particularly important to that the database support a unified data model.

There was much debate in the early 1980s over the then-novel concept of combining geometric data and its associated connectivity data in a single database. Yet taking that step enabled some of our most significant algorithms advances including connectivity-based editing, place-and-route, physical synthesis, and efficient physical verification. The time is right for a next-generation unified database.

Unified data model

Nanometer design requires a unified data model – a single design representation that can contain all information about every aspect of design, including schematic, netlist, and layout representations; digital and analog representations; and cell-based and custom representations. It must also support all associated information for these design representations, including physical layout, logical and physical connectivity, extracted and reduced parasitics, timing constraints, and detailed manufacturing data, such as OPC and PSM.

A unified database enables all design tools to operate off of a common representation, eliminating time-consuming and error-prone file transfers. Each application can focus on only the relevant parts of the database – as developers add new data types, only those applications that need the new data need to change. With today’s interchange formats, every application must understand, store, and output all information contained in the format – often resulting in information loss. A unified database eliminates such loss as each tool reads, reinterprets, transforms, and writes it (see Figure 15).

Figure 15: Nanometer database with unified data model

A unified database allows for new algorithms that use design intent currently only accessible to specific tools.

For example, an OPC creation tool can examine the slack on each signal before selecting which correction to apply, reducing mask complexity and cost. Another example includes intelligent mixed-signal design partitioning, simulation, and analysis.

A nanometer database should support advanced constructs for nanometer physics and manufacturing, such as area fill, wire slotting, OPC, and PSM. Explicit support for OPC and PSM constructs, for example, means that a single design file can include the pre-OPC/pre-PSM layout along with the OPC/PSM changes. Design teams will then be able to migrate to new manufacturing processes from the original layout more easily. Explicit constraint support ensures synchronization with the design representation, eliminating the use of incorrect constraint files. Nanometer designs will contain many different types of circuitry, including digital logic, analog, RF, memories, and programmable logic. To optimize performance and manufacturability, the database should support multiple design rule sets for a given design.

Moving forward, nanometer databases should support direct, database-level interaction with manufacturing to enable “GDSII-less” handoffs and provide important design intent that GDSII cannot represent. Mask shops could use design intent to lower tolerances for non-electrically active portions of the design such as area fill and reducing mask creation time and expense. Foundries could use design intent to optimize their processes based on specific design characteristics, perform more effective and efficient test and analysis, and optimize yield. Foundries could provide manufacturing feedback mapped to any design representation and potentially even encapsulate their increasingly complex design rules in the database.

Task 100. Look at the fig.15 and find out nanometer: data base with unified data model.

Task 101. Read the following text and try to understand the subject-matter of it.

TEXT 2F:

MASSIVE DATABASE CAPACITY AND PERFORMANCE

Nanometer databases should provide a 10x capacity improvement over the previous generation of physical design databases without degrading performance. In fact, performance on operations such as read and write need to get significantly faster. Transparent support for 32-bit and 64-bit versions of popular processors and operating systems is also important. Most designers prefer using 32-bit machines. Transportability enables them to do so for design representations within the memory limit. Designers who need to use applications beyond the 4GB limit should be able to do so without the entire design team having to move to 64-bit machines.

High database performance enables many tools to operate directly off the database, saving application development time. While some tools will use their own proprietary data structures for runtime efficiency, the persistent repository will remain the centralized database. If the database also has an appropriate extensibility model, fewer and fewer applications will duplicate structures, such as the netlist, that already exist in the database.

It is impossible to predict all future design information requirements, so nanometer databases should support the creation of new object types, the addition of attributes to existing objects, and the definition of new relationships among objects – all with native speed and efficiency. Such extensions must be lightweight, space-efficient, timeefficient, and optimized for the particular data type.

With appropriate extensibility, application developers – including in-house and third-party tool developer – can write efficient algorithms to manipulate and analyze the data they need precisely at full speed. Extensions should be available permanently to enable other tools to use them, or temporarily to serve as a coherent high-performance cache. In-memory coherence makes it possible to write tools built from cooperating components that are incremental in nature, to use lazy evaluation techniques, and to provide application-level toolkits that allow rapid new tool evolution and construction.

Nanometer databases should be open, which includes having an open application programming interface (API), open source code, and a community-based oversight committee. Openness is not a technical requirement per se, but it directly facilitates a technically superior implementation that advances rapidly. It also mitigates design team risk by enabling native third-party and in-house application development.

Task 102. Give a short summary of the text with the help of fig.15.

ACTIVITY 3